1. Field of the Invention
This invention relates generally to radio frequency receivers, and more specifically to mixer circuits that reduce second order intermodulation distortion in a direct conversion receiver.
2. Related Art
A receiver uses the frequency response of a low noise amplifier (LNA), a surface acoustic wave (SAW) filter and a duplexer to attenuate signals that are away from a center frequency of the receiver sufficiently enough so that they do not corrupt a desired signal. If the LNA and the SAW filter are removed from the analog line-up of the receiver, problems that can detrimentally affect the performance of the receiver may arise. In a transceiver, which comprises a transmitter and a receiver, one such problem is a signal transmitted by the transmitter leaking into a receive path of the receiver. In a receiver with only a duplexer to isolate the receiver from the transmitter, there is considerably less attenuation at the transmitted frequency. A receiver that lacks an LNA and a SAW filter requires additional and/or tighter constraints on at least some non-idealities in the analog line-up of the receiver. One example of a non-ideality on which a tighter constraint is necessary is the second order intercept point (IP2) of the mixer. Without a sufficiently high IP2 of the mixer, the presence of second order intermodulation distortion (IMD2) substantially reduces the sensitivity of the receiver.
Most cellular wireless transceivers use a direct-conversion receiver because a high level of integration can be obtained. However, a direct-conversion receiver requires a high input-related second order intercept point (IIP2), which is the theoretical input level at which the power of the IMD2 products are equal in power to the power of a desired signal. FIG. 1 is a simplified functional block diagram of a portion of a typical known direct-conversion receiver 102. The receiver 102 includes an antenna 106 coupled to a transconductance amplifier (TCA) 110. The TCA 110 is coupled to mixers 114 and 115. The signal path between the TCA 102 and the mixers 114 and 115 comprises two differential signal paths. An output from the TCA 110 includes differential signals IN_P 108 and IN_M 109, which are both inputted into each I-channel mixer 114 and Q-channel mixer 115. The receiver 102 also includes a local oscillator (LO) 112. One of the pair of outputs of the oscillator 112 is phase shifted by 90° by phase shifter 113 so that the mixers 114 and 115 can provide an I-phase component and a Q-phase component of the received signal. The respective outputs from the oscillator 112 are fed into the I-channel mixer 114 and the Q-channel mixer 115. The mixers 114 and 115 are employed to convert an RF signal to a zero-IF signal. The outputs from the mixers 114 and 115 are fed into I-channel baseband circuits 126 and Q-channel baseband circuits 128, respectively. The signal path for the I-channel comprises two differential signal paths, one path for differential signal I+ and one path for differential signal I−. Ideally, the differential signals should be matched, i.e., their difference should be zero. The greater a mismatch between differential signals I+ and I−, the lower becomes the IIP2 for the I-channel. Analogously, the signal path for the Q-channel comprises two differential signal paths, one path for differential signal Q+ and one path for differential signal Q−. The greater a mismatch between differential signals Q+ and Q−, the lower becomes the IIP2 for the Q-channel. The outputs from the I-channel baseband circuits 126 and the Q-channel baseband circuits 128 are fed into I-channel digital circuits 134 and Q-channel digital circuits 136, respectively. Without a sufficiently high IIP2, the IMD2 can reduce the sensitivity of the receiver 102.
Second-order intermodulation distortion products are generated when a non-ideal receiver is exposed to a two-tone continuous wave signal or to an amplitude modulated signal. In the case where interfering signals are large, very high IIP2 performance can be required to minimize signal-to-noise ratio (SNR) degradation. Non-idealities that affect IIP2 performance include device mismatch and layout asymmetry. Manufacturing process changes can also cause IIP2 performance to vary from part-to-part. Even for a particular part, IIP2 performance can vary significantly as temperature changes and with interferer frequency offset. For each part, IIP2 performance can vary with interferer offset and modulation bandwidth. To achieve consistently high IIP2 performance over many parts, calibration techniques can be employed. However known calibration techniques do not address temperature variation, can create significant DC offsets in the receiver path, can result in long calibration times that complicate system design, can degrade the noise figure, can degrade common-mode rejection ratio (CMRR) of a baseband operational amplifier (a reduction in the CMRR can significantly limit IIP2 calibration range), can be difficult or non-optimal to implement from a layout perspective, and can result in limited/inadequate calibration range.
One known approach performs IIP2 calibration at the mixers using trimmed resistors and capacitors and is limited by calibration range determined by the minimum size capacitors and resistors. This approach induces significant DC offsets. Such an approach does not address the problem of IIP2 compensation over temperature. Such an approach is based on the bipolar Gilbert cell mixer topology. The Gilbert cell mixer topology has degraded linearity performance compared to an optimized complementary metal oxide semiconductor (CMOS) topology.
Two other known approaches are based on the Gilbert cell mixer topology driving a current input load. The Gilbert cell mixer topology limits optimum achievable IIP2 performance as compared to a passive CMOS mixer and the manufacturing process cost is higher. A first approach performs IIP2 calibration before the mixers by introducing current offset at the radio frequency TCA stage. This induces significant DC offset into the receiver lineup. A second approach alters current offset in the differential oscillator buffer legs by injecting a correction current at the oscillator. This alters the duty cycle of the oscillator signal. The second approach does not work with a double-balanced mixer topology. The second approach only works for single-balanced mixer topology because the induced offset applied to the mixers is averaged out. The second approach is not applicable to rail-to-rail CMOS oscillator implementations, does not provide a rail to rail input to the mixer for optimum linearity, and does not provide common mode.
Another known approach applies correction to the bulk of the mixer devices. Some known mixers do not allow for a common-centroid layout while still maintaining each device of the mixer on a same bulk. Lack of a common-centroid layout results in degraded matching and increased IIP2. When a common-centroid layout can only be accomplished by disposing each device on a separate bulk, matching degrades because the separation between devices is greater. A high DC offset is disadvantageously created if the common mode voltage offset is induced at the mixer input, such as at the source of mixer devices. A resistor at the input adds noise to the lineup because an additional connection is unnecessarily made to the signal path. If the common mode voltage offset is forced, through a resistor, at the mixer output, a high DC offset is disadvantageously created. The resistor at the output adds noise to the lineup. Each time a calibration is done a DC offset correction may be needed, which increases calibration time. A known IIP2 optimization method merely seeks an acceptable performance, and makes no attempt to achieve best performance with minimal calibration time.
Still another known IIP2 optimization technique is performed after the mixer. With such a post-mixer technique, unbalanced differential signals that are outputted from the mixer are balanced using a post-mixer IIP2 calibration D/A converter. However, the DC offset becomes large at extreme settings of the post-mixer IIP2 calibration, which requires a large number of bits for IIP2 calibration D/A converter, and the technique disadvantageously requires that a DC offset correction algorithm be run after each IIP2 calibration. The CMRR degrades at extreme settings of the post-mixer IIP2 calibration D/A converter.
Some mixers have a voltage-mode stage following the mixer, which is non-optimal for linearity.